1. Field of the Invention
The present invention relates to a word-line driving circuit and a semiconductor memory device, and more particularly to the word-line driving circuit for the semiconductor memory device which needs a high voltage for read/write operations.
2. Description of the Related Art
In a semiconductor memory device, for a plurality of memory elements arranged in a bit-line direction for each block, a word-line driving circuit is provided for each of word lines in the block, so that the circuit may be selected in response to addressing, to drive the corresponding word line for performing write-in, read-out, and erasure operations to a corresponding memory cell.
FIG. 16 exemplifies a conventional word-line driving circuit, which is shown to comprise: P-channel type transistors 101 and 102 which constitute a flip-flop configuration switching circuit; N-channel transistors 103 and 104 which each act as a switch; a NOR circuit 105 which performs logical operations on a signal obtained by decoding high-order addresses and a signal obtained by decoding low-order addresses; and an inverter 106 which inverts an output signal of the NOR circuit 105.
In the conventional word-line driving circuit shown in FIG. 16, when both a high-order select signal BXMi for specifying high-order addresses in a memory-cell array and a low-order select signal BXSi are of a high level, the NOR circuit 105 provides a high-level output, which turns on the N-channel type transistor 103 and off the N-channel type transistor 104, which in turn turns on the P-channel type transistor 102, thus supplying a word line Wi with a power-supply voltage Vcc or a step-up voltage Vpp. When, on the other hand, either one or both of the high-order select signal BXMi and the low-order select signal BXSi are of a high level, the NOR circuit 105 provides a low-level output, which turns off the N-channel type transistor 103 and on the N-channel type transistor 104, thus disconnecting the word line Wi from the VCC/Vpp to reset it to a ground level (GND).
A circuit configuration similar to the above-mentioned word-line driving circuit is disclosed in for example Japanese Laid-Open Patent Application No. Hei9-17189.
The word-line driving circuit shown in FIG. 16, however, each requires a total of 10 transistors: two P-channel type transistors, two N-channel type transistors, four transistors in the NOR circuit, and two transistors in the inverter.
The above-mentioned semiconductor memory device requires one word-line driving circuit for each word line, a total of which circuit numbers a tremendous value with a recent-year semiconductor mass-storage device of an ever increasing integration density, so that when the above-mentioned word-line driving circuit requiring many transistors is employed, the circuitry size increases too much, thus adding to a chip size of a semiconductor IC to which a memory device is contained.
With an increasing degree of fine patterning also, memory elements which constitute a memory device is decreased in size, corresponding to which inter-word-line spacing is reduced, so that if such a small spacing between the word lines is employed in layout of a word-line driving circuit, that circuit has a poor layout efficiency of being long laterally, thus leading to a problem of a larger chip size.